現今電腦系統中，不論是桌上型電腦、手持式裝置、行動電話，處理器均扮演了一個最重要的角色。為了建立我們自有的系統晶片，我們使用可合成的Verilog硬體描述語言，開發了一個管線化的精簡指令集處理器。由於 MIPS處理器在嵌入式系統與遊戲機的普及性與廣泛使用，我們在自有的處理器裡，實作了完整的 MIPS R2000 整數指令集，包括了五十九道 MIPS指令，以五階管線化資料路徑實作、並加上前饋單元、危障偵測、分支預測等機制。此外，為了能除錯並驗證自有的處理器，我們也設計了兩個驗證環境。第一個驗證環境稱為模擬模型，以暫存器轉換階層之 Verilog硬體描述語言實作，可模擬電腦系統的完整功能。它可以協助我們的 MIPS R2000處理器在 Verilog模擬器上除錯。第二個驗證環境稱為軟硬體協同驗證環境。它是在基於 ARM Integrator與 Logic Tile的 FPGA之上來開發。這個系統可以仿真並證明我們所設計之 MIPS R2000 處理器，在 FPGA上之完整硬體行為，並掛載至 ARM Integrator系統一起驗證。設計者可藉此直接撰寫軟體來驗證 MIPS R2000處理器的功能正確性。最後，我們以 TSMC 0.13 μm與 UMC 0.18 μm的製程，用 Synopsys Design Compiler，合成我們的 MIPS R2000處理器。在 TSMC 0.13 μm製程下，其工作頻率可達 148.8 MHz，且晶片面積為
3377207.5 μm2。

Modern processor plays the most important role in all kinds of computing
domains, such as desktop computers, household appliances, mobile phones, etc. In order to build our own system-on-a-chip, we develop a pipelined RISC processor by using synthesizable Verilog HDL. Due to the popularity and widely adoption of MIPS processors in modern embedded systems and game consoles, we implements fully MIPS R2000 integer instruction set in our proposed processors. It contains fifty nine MIPS instructions with five-stage pipelined datapath, forwarding unit, hazard detection, and branch prediction mechanisms. Besides, in order to debug and verify the proposed processor, we also create two verification environments. The former verification environment is called Simulation Model, which is designed by register-transfer level Verilog HDL. It simulates the whole functionality of the computer system. It can help to debug our MIPS R2000 processor by Verilog simulators. The later verification environment is named Hardware-Software Co-verification environment, which is designed by FPGA board, Logic Tile, with ARM Integrator. This system can emulate
and prove the full hardware behavior of designed MIPS R2000 processor which is implemented in the FPGA chip, and mounted on ARM Integrator. The designer can write software directly to verify the correctness of given MIPS R2000 processor. Finally, we synthesis our MIPS R2000 processor with TSMC 0.13 μm and UMC 0.18 μm cell libraries by using Synopsys Design Compiler. The working frequency can achieve 148.8 MHz, and the chip size is 3377207.5 μm2 by applying TSMC 0.13 μm CMOS technology.