篇名 | 3D CMOS影像訊號處理器之低功耗指令設計 |
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卷期 | 148 |
並列篇名 | Low Power Instruction Set Design in 3D CMOS Image Signal Processors |
作者 | 林煌倫 、 黃柏涵 、 謝憲慶 、 溫穗安 、 唐偉翔 |
頁次 | 004-010 |
關鍵字 | 微處理器架構 、 指令集 、 三維堆疊 、 漢明距離 、 Micro Processor Architecture 、 Instruction Set Architecture 、 ISA 、 Three-dimensional Stacking 、 Hamming Distance |
出刊日期 | 201212 |
隨著可攜式3C產品的普及,照相功能已逐漸成為3C產品的基本需求,而強調可直接於產品上進行影像處理亦成為今日主流趨勢。因應可攜式裝置的需求,輕薄化概念為產品設計重要考量。三維晶片技術能有效縮小晶片尺寸,滿足影像感測產品需求。本文將介紹影像訊號處理器,於感測器平台中負責資料搬移與提供軟體修補CMOS sensor可能出現的壞點等功能,並考量指令對於處理器功率消耗的影響,提出低功率指令解碼設計,可降低位元變化率。
With the popularity of portable 3C products, the camera becomes a standard feature of 3C products, and image processing on device is also the main trend of today. For the demand of slim products, thinning is the most important design consideration. Three-dimensional chip stacking technology can effectively reduce the chip size to meet the demand of image sensing product s. This paper will introduce image signal processor which is responsible for data movement and image processing in the platform. According to the impact of dynamic power consumption, we propose a new design of low power instruction decoder, which can reduce the bit rate of change.