超低電壓和超低功率電路設計是無線傳感與物聯網路等基礎設施的關鍵技術，然而對於製程變異的敏感是超低電壓設計進入量產的瓶頸、使得超低電壓晶片錯誤率無法合乎量產標準。隨機製程變異在進入奈米製程之後已是不可避免，即使在相對成熟的65奈米，隨機製程變異已經使超低電壓電路的良率大幅降低，迫使電壓必須提昇，而難以達成能源最佳化的目標。由於時脈相關的錯誤幾乎主導了過去晶片的錯誤率，本文因此提出分離式時脈電網技術，以微幅提昇時脈電壓的方式，解決超低電壓下時脈相關邏輯閘的錯誤。根據所使用的65奈米製程， 經過晶片量測結果證實，分離式時脈電網技術成功將晶片中的微處理器操作電壓降低，達成最佳能源消耗，並且大幅提昇其在接近和低於臨界電壓操作的良率。

Ultra-low voltage and ultra-low power designs are crucial techniques of the development of wireless sensor networks and internet of things. However, ultra -low-voltage designs suffer from the sensitivity to process variations, which cause unacceptable failure rates for mass production. Random process variations are inevitable in nanometer technologies, even in relatively mature 65 nm. Random process variations have degraded the yield of ultra-low-voltage circuits implemented earlier, forcing these circuits to be operated at a high voltage and away from energy optimization. Since clock-related errors dominated the failure rate in the prior experiments, this paper presents a technique, called separate clock network voltage, which slightly boosts the clock voltage to reduce the errors of clocked cells. Using the same 65nm technology that was adopted, separate clock network voltage successfully scales down the conventional voltage limit of the microcontrollers, achieves the optimal energy consumption, and promotes the yield of near- and sub-threshold operations.