現今科技發展迅速，晶片製程的進步，使得晶片越小且越省電，而要讓晶片 效能更好、繞線更短，連接元件的路徑長最佳化，晶片中巨集電路與標準邏輯元 件的擺放佈局規劃扮演很重要的角色。我們提出新的Macro 擺置演算法，將巨集 電路分類群組，以浮動邊界來做規劃，有彈性的來改善繞線長度與擺放面積大小， 同時結合一些標準邏輯元件的擺置軟體，例如NTUplace3、NTUplace4，有效的擺 放標準邏輯元件，得出最佳化擺放結果。由實驗結果得知其效能與面積大小，皆 有效改善，大幅縮短元件間的距離。

Modern technology is advancing rapidly, and development of semiconductor process makes devices have lower power and smaller area, optimized shortest path length of the connecting elements. For this purpose, macro and standard-cells floorplan play an important role. In this paper, we present a new algorithm for macro placement to handle wirelength and macro placement area. By re-classify all macros and program floating border value, we improves wirelength and the placement area size flexibly. Experimental results show that we can improve the performance effectively by integrating our macro placer with some standard-cell placers, such as NTUplace3, NTUplace4, to minimize the macro placement area size and shorten the distance between elements simultaneously.