The primary display technology utilized by today's printers is halftoning image, and among the various image halftoning methods that are currently being used, Direct Binary Search (DBS) is the method that produces the best image quality. However, one disadvantage of this method is the requirement that images be constantly iterated, as this places many limitations on the method with respect to processing speed. In view of this issue, this work proposes an effective hardware architecture design for the DBS method that would allow for image quality to be maintained and for real-time processing to be carried out. The study proposes the application of the line buffer method to the Very Large Scale Integration (VLSI) process, so as to reduce memory usage, enable the use of a parallel processing architecture. Thus, increase the speed of the process. As results, the DBS halftoning image method was used on a gray image, and it was found that, with respect to the image, the number of iterations used and the halftone image values generated by the hardware that was updated based on the visual model error table were consistent with the results generated by software algorithms.