本研究提出一整合性電化學鍍銅之製程，結合奈米鈀催化顆粒、無電鍍銅晶種層、以及電鍍銅膜之沈積，以作為下一世代超大型積體電路銅內連線金屬化製程之用。本研究顯示，藉由敏化活化法，可以得到均勻分佈、尺寸約只有10奈米之鈀催化顆粒;以此奈米鈀催化顆粒作為成核點，可於其上以無電鍍法沈積平坦、連續、且厚度約只有30奈米之銅晶種層;之後再以電鍍法可在此銅晶種層上沈積銅膜，而此電鍍銅膜表面粗度小、電阻率只有1.77μΩ-cm、且具有非常好的填充能力，非常適合銅內連線之用。此外，本研究以四點彎曲法量測並探討此銅膜和碳化矽蝕刻阻障層之間的界面附著強度及界面剝離機制;測試時，裂隙沿界面進入，但受到延性之銅膜鈍化，所測得之界面強度隨測試速度而有所不同，約介在1.5至5.0J/m2之間，且與界面剝離速率呈現一指數關係。

An electrochemical copper (Cu) metallization process has been
developed in this study for the application to ultralarge-scale integrated
(ULSI) circuits by integrating palladium (Pd) catalyzation, electroless Cu
plating, and Cu electroplating. Uniformly distributed Pd catalysts of only
about 10 nm were firstly obtained on a Si/SiO2/TaN substrate by
sensitization and activation. A smooth and continuous Cu seed layer of 30
nm thick was then electrolessly deposited on the nanosized Pd catalysts. A
Cu film with a small surface roughness, low electrical resistivity of 1.77
μΩ-cm, and good gap-filling capability was achieved by subsequent
electroplating on the Cu seed layer. The interfacial adhesion energy and
delamination behavior between the Cu film and silicon carbide (SiC) etch
stop layer have been investigated by a four-point bending test. During test,
cracks irregularly propagated along the interface with blocking by the
ductile Cu film. The measured adhesion energy of about 1.5-5.0 J/m2 was
affected by testing velocity and showed a power-law expression to the
interfacial delamination rate.