在進入深次微米時代的超大型積體電路設計，低功率及高效能已成為最普遍的設計需求。為了達到這個目標，我們經常採用邏輯閘控制時鐘的概念。但也因此，我們必須能夠建構多個時鐘樹（其來源為同一個時鐘），並控制各時鐘樹彼此之間的時序差異。經過許多實驗分析，我們完成了一個時鐘樹建立指引，佈局設計工程師根據此指引，可順利控制單一時鐘樹的時序差異，大幅縮短時鐘樹設計的時間。實驗結果顯示，在零點三五微米製程，我們的方法可以有效將時序差異控制在0.1 ns以下。同時，我們也提出一個有系統的方法，可以有效建構多個時鐘樹，並控制各時鐘樹彼此之間的時序差異。實驗結果分析，我們的方法確實可以有效的建構多個時鐘樹，確是一個可靠的設計方法。

　　　　　In deep sub-micron era, an ASIC chip may contain milions of gates and have the requirements of low power and high performance. The ability to construct multiple clock trees effectively is very important.After conducting many clock tree synthesis experiments, which explore various configurations of clock tree structures and layouts, a guidance for clock tree synthesis is generated. By applying this guidance, the clock tree design procedure is simplified and the design time is shortened. This methodology has been used to implement clock trees on the chips designed in the Computer and Communications Research Laboratories. Our experience shows that for single colck trees the intra-clock skew is confined within 0.1ns in one design pass for 0.35 μ CMOS technology chips. For multiple clock trees, which are originated from the same clock source, the inter-clock skew may also be controlled easily. This design methodology is proved to be an effective method to implement clock trees on ASIC chips.