篇名 | 系統晶片測試之掃描鏈重序設計 |
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卷期 | 23 |
並列篇名 | The Design of Scan Chain Reordering for System-on-Chip Testing |
作者 | 王維倫 |
頁次 | 111-120 |
關鍵字 | 系統晶片測試 、 掃描鏈 、 線性迴授位移暫存器 、 重新排序 、 System-on-chip 、 Scan chain 、 Linear feedback shift register 、 Reordering |
出刊日期 | 200902 |
在測試標準IEEE 1149.1與IEEE 1500中掃描鏈(scan chain)佔有舉足輕重的地位,雖然掃描鏈需要較少的I/O接腳,但是由於掃描鏈僅能串列傳輸測試向量(test vector)相對地會耗費較長的測試時間及較多的功率消耗(power consumption)。為解決此一問題,因此在本篇論文提出一個用於系統晶片(system-on-chip, SOC)測試的掃描鏈重序(scan chain reordering)設計方法。
Due to the limited I/O pins overhead, the scan chain design plays a very important role in the testing standards, IEEE 1149.1 and 1500. However all the test vectors are applied serially into the scan chain and then applied to the circuit under test (CUT), thus much more testing time and power consumption are taken. To solve this problem, a scan chain reordering design for the system-on-chip (SOC) testing has been proposed in this paper.