本文探討於深溝式動態隨機存取記憶體 (DRAM) 測試之際，以晶圓測試者的角度如何調整參數以尋找出可能的漏電機制，從而將訊息反應給製程端，以改善DRAM 之資料保存時間。我們同時採用兩種不同測試方法並改變不同的電壓測試參數，以確切了解產品特性，最終找出最適當的測試參數，將可能的漏電位址與原因傳達給產品生產端，以便未來提高產品良率，達成本文藉由探討資料保存時間 (data retention time) 的測試條件，進而獲得較好的產出量與品質，以及增加獲利的最終目的。

Two testing methods are used simultaneously to analyze the retention time of deep trench DRAM. Both the gate and base voltages were modulated to find proper testing conditions for the failure analysis. Proper testing conditions will provide useful messages to minimize the abnormal range required for failure analysis, which therefore helps to catch exactly the addresses with leakage and the leakage mechanisms of them. Next, the exact failed addresses can be transferred to the production line to carry out laser repairing and ultimately the product yield is possibly to be improved. Therefore, the objective of this paper is to emphasize the importance of proper parameter setting for the failure testing of deep trench DRAM, which is greatly connected to the through put of products.