由於硬體資源的限制，大多數嵌入式系統中並未實作與 IEEE 754標準相容之浮點計算硬體，而採用軟體方式以整數模擬浮點運算，因而大幅降低系統之計算效能。因此，本論文設計並實作出一套具有加法、減法、乘法和除法四則運算之浮點運算器 (FPAU)，為了提高常用之加法與減法運算，我們研發單一時脈週期演算法，並設計高速捨入 (rounding) 機制，不僅可確保計算正確性，亦可提高執行速度。乘法器與除法器則採用多週期演算法實現，以減低硬體資源之使用，並可減低整體能量消耗。根據實驗結果，搭配 FPAU的系統則可有效地提昇其浮點數運算之執行效能：加、減、乘、除法分別可提高 520%、540%、1130%、470%之效能增益，整合四種運算之複數運算甚至可達 2220%之效能提升，足見本論文所提出之適用於嵌入式系統浮點運算器之價值。

For the limitation of hardware resources, most of modern embedded systems don’t include IEEE 754 compatible floating-point calculation hardware. The performance of whole system is extremely decreased due to all the floating-point operations are simulated by software subroutines with a lot of integer operations. Accordingly, this work proposes a floating-point arithmetic unit (FPAU) design which consists of addition, subtraction, multiplication, and division operations. In FPAU, the adder and subtracter are design by our single-cycle algorithm with fast rounding mechanisms which can enhance the calculation performance and guarantee the accuracy. The multiplier and divider are implemented by multi-cycle algorithms which can reduce the hardware resources and the power consumption of whole system. According to the proposed experimental results, the embedded system with proposed FPAU can significantly improve the performance of programs which include floating-point operations. The speedups of addition, subtraction, multiplication, and division achieve
520%, 540%, 1130%, 470%, respectively. The complex number application included four floating-point operations can obtain 2220% speedup. The experimental results can support that proposed FPAU is suitable for embedded systems which are required floating-point computations.