In 3G mobile terminals the Viterbi Decoder consumes approximately one third of thepower consumption of a base band mobile transceiver. Viterbi decoders employed in digitalwireless communications are complex and dissipate large power. A low power Viterbi decoder isdesigned in circuit level using self reset logic and wave pipelining technique is implemented forhigh speed operation. The Viterbi decoder consists of four units like branch metric unit, addcompare and select unit and the survivor path memory unit. All these units are designed using theself reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL inthe 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows thatthe power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83%compared to the Single Rail Domino Logic for constraint length of K =3 to 7.