隨著可攜式生醫設備的蓬勃發展，為了有效使用分配有限的電池能量，電源管理系統是不可或缺
的一環。低壓降穩壓器的電路架構包括誤差放大器電路、疊接式電流鏡、帶差參考電壓所組成，低壓降線性穩壓器具有架構簡單、低雜訊、低成本的優點，對於電源管理晶片系統來說，低壓降線性穩壓器是一個非常重要而且廣泛應用的單元。本次使用TSMC 0.35um CMOS 標準製程技術。在工作電壓2.3V~3.3V 下，輸出電壓為1.8V，最大負載電流為120mA，模擬PSRR 效能的結果
為：1KHz 的電源拒斥為-48.2dB、10KHz 的電源拒斥為-32.4dB；3.3V 下TT 溫度係數為7.72ppm/oC，2.3V 下TT 溫度係數為6.42ppm/oC，總晶片面積為0.676×0.567mm2。

With the increasing demanding of portable biomedical devices, how to use the battery energy efficiently is the most concerned problem. Therefore, power management system is indispensable for modern consumer products. For power management system, Low-dropout (LDO) liner regulator is the most common block due to the characteristics, such as simplicity, small board space, low noise and cost. The proposed LDO implemented with a standard TSMC 0.35um Mixed-Signal 2P4M Polycide 3.3/5V process technology. Supply voltage 2.3V~3.3V, Output Voltage 1.8V. The simulation results show that maximum load current of 120mA, with 2.496mV/V line regulation and 9.525μV/mA load regulation; input range 2.3V and 3.3V, the LDO has temperature coefficient 6.42ppm/oC and 7.72ppm/oC respectively. The active area of this LDO is 676×567μm2. Keywords：LDO, line regulation, load regulation, Temperature