Wavelet-based methods are mostly used for electrocardiogram (ECG) compression. By decomposing an ECG signal into multilevel wavelet coefficients, post-hoc encoding reduces the number of data bits for which the morphological characteristics can be still retained. ECG compression has a regular, data-independent manipulation that benefits implementation of very-large-scale integration (VLSI). This paper proposes VLSI architectures for ECG compression/decompression based on 3-level lifting discrete wavelet transform, bit-field preserving, and running-length encoding/decoding. The proposed architectures were implemented using Verilog hardware description language and verified in the Simulink and field-programmable gate array through the System Generator. Based on the MIT/BIH arrhythmia database, the compression ratio was 6.06 ± 0.22 with an accepted rate of 98.96% by a cardiologist when the lengths of the preserved bit-fields were set to 6, 4, 2, and 0 for the a3, d3, d2, and d1 wavelet coefficients.