In this paper, we present an efficient recursive formulation and systolic implementation of polynomial basis finite field multiplication over GF(2m) based on irreducible all-one-polynomials (AOP). Using the property of irreducible AOP we have obtained a scheme of computation-free modular-reduction up to degree m, where reduction of degree is achieved by cyclic-left-shift operations. In the proposed systolic architecture, the cyclic-left-shift has been achieved by appropriate reordering of input lines in the processing elements (PEs). Compared with the previously existing systolic structures, the proposed one is found to involve significantly less number of registers and requires nearly half the area-time complexity. It is shown that the proposed structure requires nearly the same number of gates as those of the existing bit-parallel structures.
Unlike the existing bit-parallel designs, it does not require rewiring of input lines, and critical path of proposed structure does not increase with the field order m. For m > 17 (which is required in most practical cases), the proposed systolic design is found to have significantly less area-time complexity compared with the existing bit-parallel structures.