There are two popular approaches for designing polynomial basis (PB) multiplier over GF(2m) with concurrent error detection (CED) capability to resist fault-based cryptanalysis, i.e., the parity checking and the REcomputing with Shifted Operands (RESO) approaches. The RESO approach is suited to VLSI chips. However, the systolic PB multiplier using the RESO approach will unavoidably break the regular structure when detecting errors occurred on feedback lines. The parity checking method for single parity bit can be easily extended to the one with multiple parity bits. However, the drawback of a parity checking method is the dependence on multiplier architectures, and can detect only odd number of errors. To overcome these problems, we present a novel approach, termed self-checking alternating logic (SCAL) approach, to detect errors in a systolic PB multiplier. The proposed SCAL systolic PB multiplier can keep the regular structure and takes less time overhead than existing PB multipliers with CED also. Moreover, the proposed one has the self-testing property which can ensure that there is at least one input can detect the occurred fault.