The limited applications of fuzzy logic in engineering are attributed to low computational performance of fuzzy processors. Fuzzy processors are generally unsuitable to applications which demand quick output. The speed bottleneck of these processors lies in the calculation of matching degree (MD) between the fuzzified input and the antecedent MF in inference processing. The MD calculation always needs very high latency and limits the overall inference performance. In this work, a novel VLSI architecture of a MAX-MIN circuit, for calculating the MD between the triangular shaped fuzzified input and the antecedent memberships has been proposed. The architecture developed is area, power and speed efficient in comparison to existing architectures using trapezoid and Gaussian shaped membership functions (MF). This can be attributed to the significant reduction in the number of multiplexing and subtracting operations in the proposed architecture. The FPGA implementation report has revealed that the proposed MAX-MIN calculator circuit consumes 69.2% reduced number of slice latches, 23% reduced number of input-output buffers (IOB) and the average fan-out has increased by 1.5% in comparison to a Trapezoid MF based MAX-MIN calculator circuit. Further, based on the proposed architecture of MAX-MIN calculator, novel architectures of fuzzy decoder, fuzzy inferencing system, defuzzifier and a complete fuzzy inference processor have been designed and developed. These architectures have been implemented in XILINX and Vertex field programmable gate arrays (FPGA). It has been observed that the proposed triangular MF based fuzzy inference processor is area and speed efficient, as it consumesˍ2% reduced number of 4 input look-up tables (LUT), 23% reduced number of bonded IOBs, 66.6% reduced number of global clock buffers (BUFG) and has 3.48% increase in fan-out in comparison to a Trapezoid MF based fuzzy processor.