在三維積體電路設計中，動態隨機存取記憶體扮演著不可或缺的角色，JEDEC於2011年發表 寬輸入輸出動態隨機存取記憶體標準(JESD-229)， 被視為未來可能應用於三維積體電路系統設計 的記憶體標準之一。寬輸入輸出動態隨機存取記憶體標準的目的，主要在解決傳統記憶體在傳輸 頻寬及容量不足的問題。有鑒於寬輸入輸出動態隨機存取記憶體可望成為未來三維積體電路系統 設計的重要關鍵，本論文提出一個應用於寬輸入輸出動態隨機存取記憶體的內建自我測試電路， 以期能解決寬輸入輸出動態隨機存取記憶體應用於三維積體電路系統晶片設計時之測試問題。

In the three-dimensional integrated circuit (3D IC) design, dynamic random access memory (DRAM) plays a very important role. Wide I/O single data rate (SDR) standard (JESD-229) was released by JEDEC in 2011 as one of the potential implementation methods of memory in the future 3D IC system design . The purpose of the Wide I/O SDR standard is to provide a high bandwidth and large capacity memory solution, which is the bottleneck of the traditional memory. Since Wide I/O SDR standard may become the key of future 3D IC system designs, a BIST design for Wide I/O DRAM is addressed here to solve the related testing issues in 3D IC designs.