在近年的研究中，新的混合式記憶體架構越來越受到重視。這種混合式記憶體架構整合應用了不同型態的記憶體架構，擷取不同型態記憶體的優點，在允許的效能負載下，達到較低功率消耗的運作目的。混合式記憶體架構主要是將動態隨機存取記憶體、非揮發性記憶體如相位變動式記憶體組合而成的記憶體架構。利用了相位變動式記憶體相較於傳統的動態隨機存取記憶體不需有功率消耗去維護資料的正確性，如此可減少大量的靜態功率消耗。在本篇論文中，我們提出在動態隨機存取記憶體中規劃緩衝區的架構，我們研究的重點是注重在配置緩衝器的大小以及針對目前中央處理器使用狀況及相位變動式記憶體和動態隨機存取記憶體緩衝區使用情形，進行資料判斷來做適當的存放位置來達到整體效能提高的效果。

In the memory hierarchy design, dynamic random access memory (DRAM) is usually used as main memory because of its low cost. However, DRAM consumes a lot of static power consumption due to the maintenance of data correction. In recent years, technique of emerging non-volatile memory such as phase change memory (PCRAM) is developed to overcome the shortage of DRAM. Therefore, a new hybrid memory architecture integrating DRAM and PCRAM attracts more and more attention. This hybrid memory architecture captures the advantages of different types of memory, to achieve lower power consumption under performance. In this paper, we proposed buffer architecture for hybrid memory and compared different methodologies for buffer adjustment. Based on the status of CPU, hybrid memory and buffer, the proposed technique can handle the data allocation and data migration problems efficiently.