對於厚度較薄之具有雙面電路的晶片 (< 100 μm) 而言，因製程限制與應用需求，切割製程的技術成為影 響超薄晶片切割品質的關鍵因素，國內僅有少數技術領先的半導體廠商具備此技術。切割後的晶片之側 面、背面與正面會因切割刀具、切割方法及晶圓膠膜材料等因素而影響晶片的品質，在晶片切割面的崩缺 與殘膠及正面與背面的污染微粒等瑕疵而影響產品的生產良率。因此，必須檢測每顆晶片的多個面來確保 產品的品質，及回饋產線晶片製造的品質狀況，以利於晶片品質的控管及進行製程的調整。晶片多面視覺 檢測系統為因應半導體廠的封裝製程之檢測需求，期在進行封裝程序之前即儘早的先將不合格晶片加以篩 檢剔除，故而設計於切割完成的晶圓進行晶片挑揀的過程中，以高解析光學取像裝置擷取每顆晶片多個面 的原始影像，並以影像處理與瑕疵檢測方法及其軟體完成每顆晶片的即時品質篩檢與分類。本文提出的晶 片多面視覺檢測系統，係採取以多組取放頭吸住多顆晶片進行同步移動的取像架構，分別對不同晶片的正 面、背面及四個側面進行同步取像與即時檢測。因晶片的正面與背面之影像具有較大的資料量，檢測所需 的解算時間較長，故其取像位置設於第一與第二取像站位，以利於系統可在每顆晶片完成最後一個側面的 取像與檢測之後，即時完成每顆晶片的品質判定，系統具有高效能的即時檢測之特點與優勢。所開發的光 學檢測系統具有大 FOV 與高空間解析度的運用特色，受檢晶片之最大尺寸可達 7.2  6.8 mm，瑕疵檢測 之檢錯率可小於 5%、尺寸精度可在 1 像元 (pixel) 內。開發完成之晶片多面視覺檢測系統已運用於相關半 導體產業，可在晶片從切割完成的晶圓進行挑揀的過程，完成多個面的影像擷取與瑕疵檢測，以利於晶片 的品質追蹤，及可降低後續人工篩檢的時間與成本，以提高封裝製程之效能。

For the thinner chips (< 100 μm) with circuit design both on their front and back sides, the techniques of cutting then become the critical factor of cutting quality for these thin chips due to limitation of manufacturing processes and application requirements. But only few semiconductor companies with advantaged technologies own these cutting technologies. Defects of chipping and glue could exist on chip surfaces of front, back and edge sides after cutting induced by cutting tools and methods, and fi lm material of wafer. These defects might impact quality and yield rate of chip production. Therefore, multiple surfaces of chips have to be inspected to ensure their quality of production lines, and then feedback the chip quality information for improving the manufacturing processes as well. To satisfy the inspection requirements of screening out the unqualified chips during the sorting process, an AOI system is designed and implemented by multiple optical imaging devices with high spatial resolution for image acquisition and defects detection for multiple surfaces of each chip. And chips are re-allocated on target wafer (GO) or put in tray (NG) in real-time for classifi cation. Here we proposed an acquisition architecture with multiple pick and place heads for sucking these inspected chips moved synchronously to acquire the images on front, back and 4 edge surfaces for different chips at their corresponding stations, and then inspect their defects. The computing loading of defect inspection for front and back sides of chips is larger than 4 edge sides. So the imaging sequence for these 2 sides of chips is allocated at the fi rst and second stations respectively, and then 4 edge sides of chips. Thus system can accomplish the inspection for all surfaces of each chip and real-time determine the quality of chips before put onto target wafer. Developed inspection system has features and advantages of real-time inspection with high throughput during chip sorting process, and easily adjustment and calibration for all optical imaging devices to inspect different types of chips. Developed AOI system has characteristics of large FOV and high spatial resolution for applications. The size of inspected chips can be 7.2  6.8 mm maximally. The overkilled rate of inspection can be smaller than 5%, and the accuracy of inspected defect size can be within 1.0 pixel. The sorter integrated with developed AOI system has been sold to semiconductor manufacturers, and applied for real-time inspection and quality assurance and tracing of chips. Moreover, the time and cost for manual inspection can be reduced substantially, and the effi ciency of packaging can be improved as well.