The discrete wavelet transform has gained the reputation of being a very effective signal analysis tool for many practical applications. However, due to its computation-intensive nature, current implementations of the transform fall short of meeting real-time processing requirements of most applications. This paper describes a parallel implementation of the discrete wavelet transform and its inverse using high-density field programmable logic devices (FPGAs). The implementation exploits the lookup table-based architecture of Virtex FPGAs, by reformulating the wavelet computation in accordance with the distributed arithmetic algorithm. Performance results show that the distributed arithmetic formulation results in a considerable performance gain compared with the conventional arithmetic formulation of the wavelet computation. Finally, we show that the FPGA implementation outperforms alternative software implementations of the discrete wavelet transform.