本論文將提出一操作於500MHz-2.5GHz之可程式化脈波寬度控制迴路。運用我們所提出之電路技術，可以確保輸出時脈工作週期為50%，也可以達成輸出時脈與輸入時脈間之相位同步調整。此外，在所提出架構中不需提供額外工作週期為50%的參考時脈作為校正使用，並藉由加入三角積分調變技術將可以大幅降低工作週期誤差量。而此可程式化脈波寬度控制迴路也可運用在需要可調整式工作週期應用中，例如分時式類比數位轉換器、交換式電容電路等。此次實體晶片製作採用台積電90奈米互補式金氧半導體製程，功率消耗與晶片耗費面積分別為50mW與430umx280um。而輸出時脈工作週期則能從12.5%~87.5%操作，且最小工作週期改變量為0.0488%。

A 500MHz-2.5GHz programmable pulse-width control loop (PWCL) with variable duty cycle of output clock is presented. In this proposed circuit, the reference clock with 50% duty cycle can be eliminated.
However both the requirements of 50% duty cycle of the output clock and phase alignment between the reference and output clocks can still be achieved. A 2nd-order Δ-Σ modulator is used to reduce the duty cycle
error and fulfill the requirement of adjustable output clock to the applications such as time-interleaved analog-to-digital converters and switched-capacitor circuits. The proposed circuit has been fabricated in a
90nm CMOS process. The power consumption is 50mW and the die area of the core circuit is 430umx280um.The duty cycle of the output clock can be adjusted from 12.5% to 87.5% in steps of 0.0488%.