本論文針對工研院晶片中心發展的PACDSP處理器，提出一個指令層級功率模型之建立方法。由於低階功率分析方法需要完整的硬體資訊，分析功率的過程也需要冗長的等待時間。指令層級功率分析(Instruction-level power analysis；ILPA)提供抽象化的功率分析方式，能大幅縮短執行所需等待時間。由於PACDSP處理器擁有龐大的指令集數量以及其超長指令集(Very Long Instruction Word；VLIW)架構，這些特點同時也提升建立功率模型的複雜度。本文提出的功率模型對於這種複雜的硬體架構有特別的處理方法，透過執行BDTI(Berkeley Design Technology, Inc.)benchmark的分析結果與功率分析軟體Synopsys PrimeTime PX比較，誤差率在4%以內。

In this paper, we propose an instruction-level power modeling methodology for the STC/ITRI PACDSP. Traditionally, low level and detail hardware information is needed for power estimation in which the long computing time is not acceptable. The techniques of Instruction-level power analysis (ILPA) can be used reduce waiting time greatly because of the analysis is performed on higher abstraction level. However, the PACDSP has huge instruction set together with Very Long Instruction Word (VLIW) architecture. Thus the power modeling complexity will be increased. In this work, an ILPA based power modeling for VLIW architecture is proposed. The experimental result of BDTI benchmark shows that, compared with Synopsys PrimeTime PX, the deviation is less than 4%.