本論文描述一正交電荷域濾波器，此電路同時提供降頻濾波與正交訊號分相功能。藉由輸入相位之控制，此正交電荷域濾波器可針對需求之信號提供帶通濾波器功能，而針對非需求訊號提供帶拒濾波器能力，形成一可雙程式設計之濾波器。正交電荷域濾波器在一定義的取樣頻率與一特定的輸入頻率下，其可以被使用作為正交分相器。此外，在經由次諧波取樣與有限脈波濾波器參數的選擇，正交電荷域濾波器可以作為一降頻混波器與反假像雜訊濾波器，以利於射頻接收器應用。此濾波器在使用1072MS/s取樣頻率與訊號相位選擇條件下，於反相訊號輸入時，量測結果
顯示45dB的截止頻帶抑制能力、27.1dB假像頻帶拒絕能力、36MHz的工作頻寬；於同相訊號輸入
時，量測結果顯示31.3dB內頻帶雜訊抑制能力。此晶片設計使用ESD電路於1.2V電壓，總共消耗
8.7mA功率電流；晶片實現於90奈米CMOS數位製程，總共消耗了0.98mm2晶片面積。

A quadrature charge-domain filter (QCDF) for frequency down-conversion and filters is proposed. The QCDF, based on phases of input signals, can provide a stop-band filtering and support an in-band filtering, to fulfill a dual programmable filter. The QCDF can be a splitter by selecting the input frequency and employing a specific sampling rate. Through subsampling operation along with FIR-filter coefficients, the QCDF provides a frequency down-conversion and anti-alias filter (AAF) for RF receivers. The QCDF is measured by using a 1072MS/s sampling rate and by selecting the input phases. Under the condition of a differential signal, the chip shows 45dB stop-band attenuation (SBA), 27.1dB alias-band rejection (ABR), and 36MHz bandwidth. Based on the condition of an in-phase signal, the chip shows 31.3dB in-band suppression (IBS). This chip with ESD circuits consumed 8.7mA current on a 1.2V supply and occupied 0.98mm2 in 90nm CMOS process.