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| 篇名 | 0.48V超低電壓動態影像壓縮之65奈米製程系統晶片 |
|---|---|
| 卷期 | 152 |
| 並列篇名 | A 0.48V ULV Video-Encoding SoC in 65nm CMOS |
| 作者 | 楊凱鈞 、 楊登傑 、 陳景文 、 孫際恬 、 朱涵筠 、 黃柏森 、 魏秉忠 、 蔡佩容 |
| 頁次 | 094-101 |
| 關鍵字 | 超低電壓 、 超低功耗 、 系統晶片 、 近臨界電壓 、 Ultra-Low Voltage ； ULV 、 Ultra-Low Power ； ULP) 、 System-on-a-Chip ； SoC 、 Near Threshold Voltage |
| 出刊日期 | 201308 |
中文摘要
設計系統晶片的發展過程，常常有從高性能運算同時保有完整擴充性，進展到必須能以極低 功耗延長運作與待機時間的需求，這些需求需有不同操作模式與相對應的電源管理模式。過去有 許多低功耗的IP開發例，而本論文則是論述國內第一顆成功整合H.264動態影像壓縮系統晶片，其 以台積電65奈米低功耗CMOS製程，並運用多種軟硬體與電路省電技巧，所設計出超低電壓動態 影像壓縮晶片與系統。實測結果顯示超低電壓區域最低操作電壓為0.48V，功耗為0.57nJ/Pixel。
英文摘要
The requirements of SoC design have evolved from high computing power with full extensibility to ultra-low-power consumption, such that the system can be operated with resilient stamina and longer stand-by period. Additionally advanced power management is required to meet different operating modes. In the past there were a lot of IP design examples which demonstrated the features of low power consumption. In this work a fully integrated H.264 motion picture encoder is implemented and it is the first low power SoC of its kind and is fabricated with TSMC 65nm low power CMOS process. Various power saving technologies in hardware design and firmware control are applied in this SoC design. The field trial has shown a minimal of
0.48V operating voltage which the computing core is operated in ultra-lower-voltage regime, and the corresponding power consumption is at 0.57nJ/Pixel.