許多論文針對數位電路的電源網路設計與雛型作研究，然而尚未有一個有用又實際的設計被 提出。本研究會著重於如何在邏輯晶片上面生成一個可以通過商業工具驗證的電源供應網路。本 研究整合了邏輯晶片上的電源供應網路分析、優化以及生成，並考慮了熱效應以及電源供應板的 位置所造成的影響。此外，也採用最大流量演算法來解決這個設計階段中所違反之設計規範驗證。 在生成電源供應網路之後， 本研究會建立一個基於節點電壓、線電阻以及金屬層之間的via 電阻的靈敏度矩陣。並利用序列線性規劃法(Sequential Linear Programming, SLP)來迭代調整 靈敏度矩陣，直到IR-Drop滿足所設的條件。最後，本研究採用一個基於TSMC 65nm LP製程的 實際電路來測試所提出的演算法，其IR-Drop可以降低到供應電壓的2%以內。

There are many works on the power network design and prototyping for digital designs, however some usual and practical design concerns are not addressed. In this work, we present a realistic power network design methodology without IR violation certified by state-of-the-art commercial tool. Our work integrates analysis, optimization and synthesis of power network. In particular, we consider thermal effect and power pad’s positions during the prototyping of power network. A scenario in placement regarding the violation of design rules is considered and resolved by maximum flow algorithm at the same stage. After the synthesis of initial power network, we generate a sensitivity matrix which is correlated with nodal voltage and resistances of net and via in metal layers. Furthermore, a Sequential Linear Programming (SLP) will be applied to adjust the sensitivity matrix iteratively until the IR drop constraint is satisfied. Our work is experimented on a real design in TSMC 65nm LP process, and the result validates our framework that the IR-Drop can be reduced to 2% of supply voltage.