The key performance of many analog integrated circuits is directly related to capacitance ratios. Lower variance of capacitor ratio will result in higher yield. This study presents the placement generation of the unit capacitors with the lower variance. This study shows that the unit capacitors place as close to the central entries of the array will result in lower variance. To accomplish this, a partitioning scheme with a set of merging rules is proposed. The resultant placements achieve lower variance of capacitor ratio and thus improve the yield from 74% to 88% than the previous works.