篇名 | 3D IC異質堆疊介面設計與自我測試架構 |
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卷期 | 148 |
並列篇名 | Design of Interfaces between ISP and ADC array and Self-testing Architecture in 3D IC |
作者 | 唐偉翔 、 黃柏涵 |
頁次 | 011-015 |
關鍵字 | 異質介面 、 自我測試 、 序列轉平行轉換器 、 Interface of heterogeneous circuit 、 Self-testing 、 Serial to Parallel Convertor 、 S2P Convertor |
出刊日期 | 201212 |
隨著3D IC技術發展,異質電路整合成為必然的趨勢。此篇文章介紹ADC與ISP Array堆疊介面設計,其內容含訊號格式轉換、自我測試機制與效率分析。根據模擬顯示此電路在每條Line上提供99.246%的效率,加上自我測試機制面積僅增加0.6%。
When the technology of stacking IC goes mature, integration between heterogeneous circuits becomes feasible. This article introduces the design of the interface between ADC and ISP array and contains signal transformation, self-testing and analysis of efficiency. According to the simulation result, the interface possesses the 99.246% efficiency to transform and fulfill signal of one line buffer. The area overhead is merely 0.6% to equip the self-testing circuit in a certain ISP.