三維晶片因為擁有封裝密度高的優勢與異質整合時的設計彈性，儼然已經成為近來重要的新興技術。而其中，穿矽孔的擺放位置是三維晶片設計的重要關鍵技術之一。為了能達到更高的效能，三維晶片採用穿矽孔來垂直連接多個二維晶片，但卻因此而遭遇到隨機斷路瑕疵和熱機應力等的問題。這些潛在的良率損失可能會顯著地提高量產成本，繼而影響到三維晶片的利潤。為了增加穿矽孔的可靠度，雙重穿矽孔、共享備用穿矽孔以及穿矽孔容錯單元等技術因應而被發展出來。在本文中，我們簡單地探討這些技術的特徵，並藉由三維時脈架構來比較他們的效能與成本。

Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. The potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. To address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. In this paper, we briefly discuss the TSV fault tolerant techniques and use 3D clock networks as a vehicle to compare their effectiveness and overhead.