儘管三維晶片（3D ICs）具有提供現代電子裝置各種好處的潛力，但時下商用軟體工具目前仍舊處於一次只能實現一層的矽佈局；垂直堆疊晶片協同最佳化的能力受到極大的限制。其中，部分肇因於它們於三維晶片的實現上依然借用二維晶片的設計／實作型式；然而，堆疊晶片間的時序、功率與面積協同最佳化是無可避免的。在本文中，我們將呈現如何適當的改變設計方法來達到堆疊晶片間的效能最佳化。最後，實驗結果將指出所提出的技術方法可以減少許多繁雜重複的工作程序，有助於增進實現三維整合的步調。

Even though 3D integrated circuits (ICs) potentially provide modern electronic devices with various advantages, present commercial tools realize silicon layouts one at a time. The capability of stacked-die co-optimization remains largely restricted. This is, in part, due to the leverage of 2D IC design/implementation styles. Inter-die co-optimization is imperative for 3D ICs where timing, power, and area are simultaneously considered. In this article, we show how to enable stacked-die co-optimization with the proposed adaptive buffering technique. Empirical results indicate that the proposed approach reduces many routines, which can help hasten the pace of realizing 3D integration.