穿矽孔是三維積體電路最重要的元件之一，因為它構成晶片與晶片之間的垂直連線。但是它的兩端唯有在晶片黏合之後才會完整地連結，因此，一般以為直到此時才得以測試，無法在晶片黏合之前預知穿矽孔是否良好。本文中我們提出一個全新的策略，專門用來測試在晶片黏合之前的穿矽孔。此策略借用動態記憶體(DRAM)常用的感測放大技術來執行晶片中穿矽孔的監控。我們運用其固有的電容特性，可以用很少的面積就可以偵測出待測電路中錯誤的穿矽孔。

Through silicon via (TSV) is one of the most important devices for 3D ICs to enable vertical interconnection among stacking layers. Because two ends of a TSV are completely connected only after bonding, it is often thought that there is no way to monitor the quality of TSV before bonding. We present a novel TSV testing scheme by performing on-chip monitoring before bonding, using a sense amplification technique that is commonly seen in a dynamic random access memory (DRAM) circuit. By virtue of the inherent capacitive characteristics, faulty TSVs can be detected with little area overhead for the circuit under test.