本文介紹一個實現於台積電0.18微米CMOS製程，應用於無線感測網路節點中之喚醒接收機。在相同的偏壓電流消耗之下，本文所提出之電流再利用射頻前端電路架構和傳統疊接架構相比，其電壓增益可至少增加10dB。如此可使整體喚醒接收機在最低的電流消耗下提供最高的電壓增益，亦使其在超低功率消耗之下保有高靈敏度偵測之性能。喚醒接收機操作在0.5V低電壓供應之下，其整體電壓增益超過55dB,前端線性電路之雜訊指數低於18dB，且平均功率消耗低於30uW。此喚醒接收機支援2.4GHzISM頻帶,晶片面積為0.53平方毫米。

This article introduces a Wake-Up receiver applied for wireless sensor network in TSMC 0.18 um CMOS technology. The voltage gain of RF front end circuit is improved for more than 10dB by proposed current Re-Use topology compared with conventional cascode topology under the same current consumption. Thus, the proposed Wake-Up receiver achieves maximum voltage gain at lowest current consumption, and keeps high sensitivity performance with Ultra-Low power consumption. The supply voltage of Wake-Up receiver is 0.5V, overall voltage gain is larger than 55 dB, noise figure of linear front end is lower than 18 dB, and average power consumption is lower than 30 uW. This compact Wake-Up receiver operates at 2.4 GHz ISM band, and the chip size is only 0.53 mm^2.