由於製程技術的快速演進，引領IC設計進入SoC系統單晶片(System On Chip; SoC)時代，造成電路大小的急劇增加，也導致設計上的複雜度、成本、與流程的連續演變。軟硬體同步設計／同步驗證與高設計抽象級設計方式，是近幾年IC電路設計演化過程中的趨勢。而高位合成技術(High-Level Synthesis; HLS)，可以協助IC設計者同時完成上述關鍵。於本篇報告中，將呈現－NAND快閃記憶體控制器之高位合成設計實例，從實驗結果得知此技術可以幫助達到設計彈性並縮短整體軟硬體開發時程。

Improvement of IC manufacturing technology leads the IC design methodology into the SoC era. Due to the growing of design size, complexity and Design-Cost, IC design flow would continuously evolve. Hardware and software Co-Design/Co-Verification and high abstraction level design are two key points of evolution on design flow in recent years. Methodology of high level synthesis would help designer to achieve these points simultaneously. In this paper, an IC design case of NAND Flash controller using high level synthesis would be shown. Experiment results approve that high level synthesis could bring us the benefit about flexibility of design and shorten of development.