CPF/UPF為EDA業界因應電子電機產業低功耗需求而發展出來的統一功率管理格式，這種格式用以提供使用者在不同供應商的工具流程中，描述低功耗設計構想。此篇論文中，我們以本所之65nm Media Platform IC(MPIC)為實現載具，詳細探討低功率設計流程。載具中包含了高效能數位訊號處理核心(PACDSP)、功率管理單元和內建熱感應器以量測晶片溫度，並可藉由橋接器搭配FPGA發展平台，作為多核心的發展雛型。此多媒體平台具有四個電壓區域，利用特製的功率管理單元和DVFS機制，達到多重功率操作模式及可適應性電壓控制；並可藉由統一功率管理格式來貫穿整個流程。從閘級設計驗證到實體驗證，包含功率架構驗證、時序驗證、功耗分析、正規化驗證、動態模擬、平面與電源規劃、時鐘樹設計、繞線、訊號與壓降分析、設計製造及實體驗證等，皆能滿足65nm Media Platform IC (MPIC)設計規格，並成功下線。這足以證明我們所建立低功率實現與驗證方法之完整性。

The Common Power Format (CPF) or Unified Power Format (UPF) is an commonly used industry standard format that can be utilized to describe the power constraints in an electronic circuit. In this work, our ITRI 65nm Media Platform IC Chip is used as the test vehicle to evaluate and integrate the CPF and UPF to the low power design flow. This platform consists of a PACDSP (Parallel Architecture Core DSP), a PMU (Power Management Unit), 9 thermal sensors, and an FPGA chipset. Inside the PACDSP, there are four power domains which can be controlled individually by the PMU. The design issues from front-end design to back-end design, including the gate-level simulation, synthesis, DfT, functional & Low Power verification, Floor Plan, CTS, APR, timing / crosstalk / power / IR-Drop analysis, DfM and DRC/LVS/ERC can be integrated throughout this format. A real chip has been successfully designed and taped-out to verify the feasibility of this design flow.