隨著半導體製程的演進，積體電路從前段設計到後段驗證程序日益複雜，佈局與製程相關參數影響電路效能的比例遽增。鑒於目前積體電路模擬在佈局前與後差異甚大，積體電路設計者時常花費多次的設計遞迴，以完成電路的最佳化。本文因此提出一快速模擬模組，於佈局之前期便能考慮佈局相依特性的電晶體非理想效應。所使用的方式是預測擴散區長度效應和井鄰近效應兩種在先進製程出現的非理想效應，計算其在BSIM4.0模型的相關參數，建構於SPICE模擬可用的模組，提供電路設計者在電路佈局前快速預測電路特性，藉以最佳化。所提出的快速計算模組，經過數位邏輯電路比較，與佈局結果相差10%以內。

As the progress of semiconductor technology, design flows of integrated circuit (IC) become increasingly complicated. Layout and process dependent effects influence the entire design flow. According to the performance difference between pre- and post-layout, IC designers usually require time-consuming design cycles for circuit optimization. Therefore, this work proposes a fast SPICE module that considers layout-dependent effect of transistors. Two non-ideal effects, length of diffusion (LOD) and well proximity effect (WPE), in advanced CMOS technologies are predicted and calculated using BSIM4.0 model. The proposed SPICE module helps circuit designers simulate the circuits with layout-dependent parameters before layout. Thus, circuit optimization accelerates. The proposed SPICE module is verified by comparing pre- and post-layout digital logic circuits. The prediction error is within 10%.