本論文提出一種使用數位式電壓穩壓器之超低電壓全數位鎖相迴路。當數位控制震盪器產生之電源雜訊頻率範圍為100-kHz到100-MHz， 此數位式電壓穩壓器可維持數位控制振盪器之280-MHz輸出訊號的抖動量均方根值小於0.55%。數位控制振盪器採用兩段式數位控制變容器，進而達到高解析度之特性。其數位濾波器提出雙緣觸發技巧，以減少面積與縮短主要延遲路徑。在低電壓的操作中，其數位控制振盪器與時間對數位碼之轉換器架構使用基極控制技術以達到高操作頻率與高解析度之優勢。當操作電壓為0.5V時，此全數位式鎖相迴路產生之輸出訊號可以達到720-MHz之操作頻率。其量測功率消耗小於570uW。本架構實現於90nm CMOS製程下，電路面積為0.02um2。因此， 低電壓操作之全數位時脈產生器可以有效的使用於低功率消耗之系統。

This paper proposes an ultra-low voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator. The digital supply regulator maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution. The proposed digital loop filter can reduce the area cost and critical path using the double-edge trigger technique. For a low supply voltage, the DCO and the time-to-digital converter use bulk-controlled techniques to increase the highest operating frequency and timing resolution, respectively. When the ADPLL output is 720-MHz at 0.5V, the power consumption and core area are 570μW and 0.02mm2, respectively, in a 90nm CMOS process. Thus, the low supply voltage ADPLL can be easily to use for low power consumption systems.