本文描述使用一8T靜態隨機存取記憶體記憶單元(Bit-cell)的讀寫線路設計。操作在低電壓時，能去除讀取位元線漏電流(Bit-line Leakage Current)，並能維持較快的操作速度。讀取位元線漏電會導致資料讀取錯誤 這種現象容易發生在低電壓系統，這會使得可操作電壓無法往下調降。尤其記憶體容量越大， 漏電也會更加的嚴重。一般為了減低位元線漏電的作法是使用2顆NMOS串接的記憶單元讀取埠(Read Port)，此種方法不僅只降低通過的漏電流，相對的也減低了低電壓時的正常讀取速度。本文的讀寫線路設計可以完全去除這種問題。另外，使用寫回電路在不寫入新資料的列(Column)，可以先讀出記憶體單元的資料，再重新寫回，以確保資料不受擾動。另外搭配穩定的控制電路及感測放大器(Sense Amplifier)， 使得電路可以操作在更低的電壓環境。根據量測結果，本文統計並分析製程變異(Process Variation)對靜態記憶體電路所造成的影響，以及提出更有效的設計方法。

In this article, a SRAM read-write circuit design using 8T memory Bit-cell is proposed. In low voltage operation, it is capable of eliminate Bit-line Leakage Current problem entirely, and keep up faster operational speed. The Bit-line Leakage Current could lead to sensing errors; that often happens in low voltage systems when there is little leg room for operational voltage to drop. The data-sensing mistake results from large bit-line leakage, especially in high capacity SRAM. The common solution to reduce Bit-line Leakage Current is by series-connecting two NMOS to the Read-Port. However, this not only reduced leakage but also slow down the access speed in low voltage operation. The proposed Bit-cell design can totally eliminate such problems. Moreover, for robust write function in low voltage operation, this SRAM is embedded with a Write-Back function. The non-written column of bit-cells in the same row fetch the original data before write operation, and then together with the write cell, write original data back to prevent data damage. This SRAM is more robust in low voltage operation, because it equipped with a stable control circuit and sense amplifier. In the last section, the measurements and results are presented, the statistical data of SRAM bit-cell due to process variation is collected and analyzed.