本論文提出一個CMOS可操作在一伏以下且無輸出電容補償的數位控制迴路的低功率消耗低壓降電壓調整器。此數位控制迴路的技術可以使得功率消耗比其他傳統的控制迴路的電壓調整器還要小，而且提出的電壓調整器不需要輸出電容補償。輸入電壓最低為0.9V，輸出電壓為0.6V，最大的輸出電流為120mA。此電壓調整器使用TSMC0.35μmCMOS製程，晶片面積（包含I/Opad）為927μm×969μm。

A CMOS sub-1V Capacitor-Free Low-Power-Consumption Low-Dropout voltage regulator (LDO) with digital controlled loop is presented in this paper. This technique can make power consumption lower than other LDOs with traditional controlled Loop. Especially, the performance of power consumption of proposed LDO without Off-Chip capacitors is excellent. The LDO can also be stable even without the output capacitor. With 0.9V power supply voltage, the output voltage is designed as 0.6V. The maximum output current of the LDO is 120 mA at an output of 0.6V. The prototype of the LDO is fabricated with TSMC 0.35-μm CMOS processes. The chip area (including I/O pad) is only 927μm×969μm.