當晶片電壓降到超低電壓範圍，處於不同電源模式間的時序收斂問題，成為了一項嚴峻的挑戰。由於晶片電壓變動的範圍極大，巨大的時序差異常常發生在不同的電源模式之間。為了要降低時脈差異，我們發現，傳統的電源感知時脈樹會造成過多的功率消耗。本篇論文所提出的可電壓控制之電源感知時脈樹結構， 可利用不同電源模式資訊， 選擇適當的操作電壓與時脈延遲通道， 在面積與功率消耗上都可獲致明顯的改善。

As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power -mode-aware clock tree often suffers from a huge overhead on power consumption. In this paper, we propose a power-mode-aware clock tree structure to select the supply voltage and the buffer chain channel at the same time ; as a result,
both the area and the power consumption can be improved.