將數位電路的電壓降低使得其功率消耗以二次方的比例縮小， 對攜帶式產品具有極大誘因，而支持超低電壓操作以及動態電壓調整的標準邏輯元件庫，是達成該目標的基礎。在一個支持超低電壓的標準邏輯元件庫中，正反器是非常關鍵的邏輯電路元件，由於低電壓使得其中電晶體驅動力降低、抗雜訊能力降低、對於製程變異敏感度提高，因此正反器必須額外的設計考量，其中牽涉到電晶體使用、電路架構、以及系統時序。本文提出以適應性複製的敏感電路時序，作為支持超低電壓以及動態電壓調整之脈衝式正反器，並介紹所使用設計方法，包含低電壓下的容忍製程變異設計、系統效能與功率考量、以及適應動態電壓調整的時序分析。

Lowering the supply voltage reduces the power consumption of digital circuits in a quadratic magnitude, which extends the lifetime of portable products. An ultra-low-voltage standard cell library facilitates the construction of low-power digital systems. In a low-voltage standard cell library, flip-flops are crucial components. Low-voltage flip-flop performance is sensitive to process variations because a low supply voltage
degrades transistor drive strength and noise immunity. Adaptive strategies in circuit design, transistor assignment, and timing analysis are required to enhance the operability of low-voltage flip-flops. Therefore,this article presents an adaptive pulsed flip-flop that duplicates the sensitive circuit path to act as a replica.This structure enhances the timing characteristics of pulsed flip-flops operated at ultra-low voltages or during voltage scaling. In addition, this article provides relevant issues about using the pulsed flip-flops, including variation-aware strategies, system performance and power trade-off, and timing analyses considering dynamic voltage scaling.