提出採用薄閘極氧化層元件設計之無電阻元件電源軌線間靜電放電箝制電路，以及搭配矽控整流器元件作為主要的靜電放電箝制元件， 並於65奈米1伏特的互補式金氧半製程中驗證。採用薄閘極氧化層元件之閘極漏電流特性，來實現靜電放電偵測電路中的等效電阻，使得電阻電容時間常數之靜電放電偵測機制可不使用實際的電阻元件，同時可降低佈局面積。根據量測結果，所提之電源軌線間靜電放電箝制電路搭配寬45微米之矽控整流器箝制元件， 可通過5kV的人體放電模式與400V的機器放電模式之靜電放電測試，而其在1V的正常電路操作條件與室溫環境下，漏電流約為1.43奈安培。

A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with silicon-controlled rectifier as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents of the thin gate oxide devices to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25oC under the normal circuit operating condition with 1V bias.