隨著電子產品往多功能、低功耗、高效能發展，有愈來愈多功能集合於系統單晶片(System on Chip; SoC)上，因此近年來的探索開始從二維平面晶片轉向三維的系統晶片設計與製造技術，又目前SoC架構中，記憶體佔了二維晶片中大部分晶片面積。本論文之技術重點在於，因應二維晶片中記憶體佔大部分晶片面積的現象，將記憶體使用堆疊的方式呈現，提出三維晶片上可調配堆疊記憶體架構，並且在進行堆疊記憶體架構探討時，考慮了堆疊記憶體所整合的位置；依據上述的分析結果，提出將堆疊記憶體區分成指令記憶體(Instruction Memory; IM)或是資料記憶體(Data Memory; DM)，其選擇方式可讓使用者自行設定，使用者可以選擇堆疊記憶體全都是資料記憶體，或是指令記憶體和資料記憶體並存，達到提升程式執行效率並提供程式開法者更具使用彈性之硬體架構；在本論文最終利用電子系統層級虛擬平台評估系統效能，證明堆疊記憶體所帶來的效益，使用堆疊記憶體和傳統二維記憶體相比，能夠得到1.468倍的加速。

Today's electronic devices are expected to be fully function, low power consumption and high performance. There are more and more functional modules integrated in a SoC chip. A three-dimension integrated circuit (3-D IC) is developed and in which two or more layers of active electronic components are integrated both vertically into a single circuit. In two-dimension IC, the memory size usually dominated and occupied the most of area. The key features of this paper are analyzing the stacking memory architecture and estimating the entire system performance and describing the reconfigurable stacking memory architecture for three-dimension IC. With the architecture exploration, we use a kind of extendable stacking memory which has the reconfigurable feature. It allows users to configure the different architectures of stacking memories for different applications. User can configure a part of memory as instruction memory and the others as data memory or treat the entire memory as data memory. We use ESL technology to demonstrate the performance improvement. It shows that there is 1.468 times of speed-up by using the stacking memory architecture.