隨著製程技術的演進，系統單晶片設計與應用亦日趨成熟，晶片中的核心數目、矽智財(IP)功能多樣化及互連系統架構複雜度更是與日俱增，傳統RTL模擬驗證效能已逐漸無法負荷日益複雜的單晶片設計。因此我們藉由原型系統(Prototyping System)提升效能並提早進行軟硬體整合驗證以縮短驗證時程，然而原型系統效能雖高於傳統RTL模擬系統卻因可觀測度不佳而造成除錯困難。論文中我們將建立一個可應用於原型系統之高觀測性驗證與除錯平台，並以工研院自行開發異質多核心原型系統平台之軟硬體整合實際案例，說明如何利用此嵌入式系統軟硬體整合驗證與除錯平台快速地進行原型系統內部偵錯及定義問題所在。

With the evolution of process, the SoC technology has become more progressive. The number of cores in one chip, the variety of IPs, and the architecture of interconnect are growing rapidly. The traditional RTL simulation environment performance has been unable to deal with highly complex SoC design. So we must use the prototyping system to increase the simulation performance and integrate hardware and software in early stage. The performance of prototyping system is higher than traditional RTL simulation environment, but the disadvantage is lack of visibility in FPGA for debugging. In this paper, we build up a high visibility prototyping system for hardware and software integration and verification. We use PAC Duo+ prototyping system as an example to illustrate how to use the high visibility environment for identify problem and debugging during hardware/software integration stage.