由於晶片整合密度的高度需求，進而發展出三維晶片技術來增加系統效能，並且在三維晶片垂直堆疊技術上，穿矽孔技術是一個非常有效的方法。然而現今穿矽孔製程的良率依然不高，因此本篇論文提出一種應用於三維晶片之穿矽孔技術的線上錯誤偵測與更正技術，並基於雙餘數編碼，藉由特徵分析來達到線上偵測與更正損壞之穿矽孔所造成的錯誤。實驗結果證明本論文所提出的架構可以改善穿矽孔的良率高達99.9%，並且不會增加太多額外的面積與穿矽孔數量。

Due to the requirement of integrated circuit density, the technology of three-dimensional integrated circuit (3-D IC) is developed to improve the performance of system and the through silicon via (TSV) for vertical stacked technology is a high efficiency methodology. However, the yield of TSV is still low nowadays. Hence, this paper proposes an on-line error detection and correction techniques for TSV in 3-D IC. The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design improves the yield of TSV up to 99.9% and has good performance in area and TSV overhead.