使用穿矽孔(Through Silicon Via; TSV)技術之三維晶片(Three-Dimensional Integrated Circuit; 3-D IC)已被廣泛認知為未來可行的積體電路技術。三維晶片包含由穿矽孔所連結的多層裸晶，可提供現行二維積體電路所沒有的優點。然而，三維晶片測試上的困難度遠大於二維積體電路。在本論文中，我們提出了測試三維晶片中穿矽孔的低成本內建自我測試電路(Built-In Self-Test; BIST)。所提出的方法將穿矽孔安排成一類似記憶體的陣列，且自我測試電路具有低的測試／診斷時間以及低的面積成本。實驗結果顯示，對於一穿矽孔大小為45um^2所形成的16×32穿矽孔陣列，在使用0.18um CMOS製程的條件下，所提出自我測試電路的額外面積比為2.24%。此外，對於穿矽孔陣列中的緊縛瑕疵(stuck-at fault)，所提出自我測試電路僅需130個測試時脈週期。與IEEE1500為基礎的測試方法比較，所提出內建自我測試方法可達到85.2%的面積成本縮減，以及93.6%的測試時間成本縮減（以16×32穿矽孔陣列為條件）。

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3-D IC including multiple dies connected with TSVs offers many benefits over current 2-D ICs. However, the testing of 3-D ICs is much more difficult than that of 2-D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3-D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18um CMOS technology; for a 16x32 TSV array in which each TSV cell size is 45um^2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500•based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.