應用穿矽孔的三維整合技術是積體電路設計近來新興起的技術。與系統晶片技術相比，三維技術可以提供多項的優點。然而，在應用穿矽孔來量產三維晶片之前，依然有些挑戰需要被克服。在這些眾多的議題中，測試是其中一個大挑戰。三維晶片可由多個不同供應商所設計的裸晶堆疊而成，所以需要一個標準化的測試界面來作裸晶之間的測試整合。我們試著開發一個標準化的測試界面，而此測試界面包含測試存取埠與測試存取機制。為了減少測試所需之輸入輸出的數目，所提出的測試控制埠完全相容於IEEE 1149.1的測試存取埠。而所提出的測試存取機制，則於三維晶片堆疊之後在裸晶之間負責傳輸測試資料。另一方面，每一個裸晶中皆需要一個測試整合的方法，來處理各個裸晶中的所有DFT電路。所提出的測試整合方法可以支援堆疊前測試、漸增式測試與堆疊後測試。此外，所提出的測試整合方法在電路板層級測試時完全與IEEE1149.1相容。

3-D integration technology using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) designs. It can provide many benefits over the 2-D integration technology. However, there are some challenges should be overcome before volume-production of 3-D ICs using TSV becomes possible. Among these issues, test is one of the big challenges. A 3-D IC consists of multiple stacked dies which can come from different suppliers. A standardized test interface thus is required for inter-die test integration. We attempt to develop a standardized test interface. The test interface consists of a test control port and a test access mechanism (TAM). To minimize the number of test IOs, the proposed test control port is compatible to the test access port of 1149.1. Also, an inter-die TAM is proposed to transport the test patterns for the post-bond test of 3-D IC. On the other hand, a test integration method for handling the design-for-testability (DFT) circuits within dies should be designed in a die. The test integration method can support pre-bond test, incremental test, and post-bond test. Furthermore, it is compatible to 1149.1 during the board-level testing.