本文提出了一種為三維積體電路設計的CMOS影像感測器(CIS)的電路和類比數位轉換器(ADC)。此設計採用模塊化設計，並提出新的讀出電路和控制方法。對應每個子陣列它只需一個微焊球(μ-bump)，而不是每個像素或每列。如此可避免在三維堆疊時使用過多接點造成的良率降低或面積過大造成的成本問題。我們提出的結構與讀出像素時的二維解碼功能實現了高解析度，且不會降低取像率(Frame Rate)。一個面積為300μm×150μm的交錯式10位元的逐次逼近(SAR)ADC也被用來讀取感測器。我們設計了一個四個子陣列（4×192×128像素）的測試晶片，每一個像素大小為2.8×2.8微米，使用台積電0.18微米CIS製程。實驗結果證明，該4個模塊成功的平行輸出每秒100幅圖像(100fps)。結果表明，通過模組化陣列設計並加以擴展，這個架構有望實現以100fps在高速高解析度攝影機的應用。另外，SAR ADC測得的DNL，INL和功耗分別是+0.59/-0.41 LSB，1.32/-0.73 LSB和130微瓦。

This paper presents a new CMOS image sensor (CIS) structure and ADC design for three-dimensional (3D) integrated imagers. A modular design of CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump (μ-bump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional decoding function achieves a high spatial resolution without degrading the frame rate performance. A 10b time-interleaved asynchronous successive approximation register (SAR) ADC was also implemented within 300μmx150μm for array readout. A prototype chip with four sub-arrays (4×192×128 pixels) and a pixel size of 2.8×2.8 um^2 was fabricated using TSMC 0.18um CIS process. The experimental results demonstrate the parallel output images of 4 modules successfully with 100fps. It shows that the array is expandable by modular sub-array design and is expected to achieve 100fps at multi-mega imaging for high-speed HDTV camera applications. The measured DNL, INL, and power consumption of the SAR ADC are +0.59/-0.41 LSB, +1.32/-0.73 LSB, and 130 μW respectively.