本文提出使用改良的多路徑延遲交換(Multi-path Delay Commutator；MDC)管線式架構，可以用以實現高效能快速傅立葉轉換處理器。該處理器可以同時計算四路獨立輸入資料，並且平均輸出信號量化雜訊比(Signal to Quantization Noise Ratio；SQNR)在43dB以上。藉由記憶體之間資料暫存與交換控制，和傳統MDC架構比較，可精簡記憶體使用達60%以上。使用以4或8為基底的蝴蝶式運算元可以縮減管線架構之級數，除此之外此處理器同時也可以將平行的序列輸入轉換為接連的區塊輸出，藉此單一後級的模組或暫存元件即可處理四路資料。另外，彈性的級數控制可計算2048，1024，512，以及128點傅立葉或反傅立葉轉換，可用於正交分頻多工(Orthogonal Frequency Division Multiplexing；OFDM)架構的產品上，例如IEEE802.16 WiMAX或LTE。最後，在實作上，使用的模組規律且簡單，在RTL設計上可重複使用且易於擴充升級。

The paper presents an efficient approach to implement a Fast Fourier Transform (FFT) processor in multi-path delay commutator (MDC) pipeline architecture. Four independent input data streams can be processed concurrently with output signal to quantization noise ratio (SQNR) above 43dB. Improved memory-swap mechanisms reduce memory size to 60% compared to that of traditional MDC designs. Radix-4 and radix-8 butterflies reduce the pipeline stages. The processor also converts parallel streamy inputs into serial block outputs so that afterwards a single functional block or FIFO can process four streams of data. The flexible stage control can configure the processor as 2048-, 1024-, 512-, or 128-point FFT/IFFT for orthogonal frequency division multiplexing (OFDM) applications, which comply with IEEE802.16 WiMAX or LTE. As for implementation, the components are regular and simple, which makes the RTL code reusable and scalable.