隨著製程微縮技術日漸困難，要跟上摩爾定律所預測的發展趨勢，必須付出的高昂成本，這已非一般IC業者所能負擔。這些狀況使得半導體業者無法輕易滿足市場對IC產品高整合、低功耗及低成本等需求。三維晶片技術的出現，適時開啟了一道曙光。藉由垂直堆疊技術，除了可使晶片尺寸變小、縮短傳輸距離以提高效能並降低功耗外，更能實現異質晶片整合。市場研究機構也紛紛預測未來三維晶片技術可大量應用在智慧型手機、平板等高階可攜式產品。此外，記憶體堆疊與及固態硬碟也都會是重要的應用領域。本文將介紹利用穿矽孔為主的三維晶片技術，並概述工研院資通所在三維晶片設計領域的投入與研發成果。雖然當前國內外產學研各界皆積極投入三維晶片技術的發展，但離技術成熟與廣泛應用仍有一大段路要走，需IC設計公司、晶圓廠、封裝測試廠及學研各界共同努力，克服挑戰。

CMOS scaling, following Moore's Law, brings incessant challenges to the semiconductor manufacturing. The cost of the advanced technology becomes too high for the IC companies. Therefore, the semiconductor industry cannot easily reach the market's requirements for IC products with high integration, low power and low cost. Three-dimensional integrated circuit (3-D IC) technology may be a means to overcome those difficulties. With it, we can have the smaller die size, the shorter signal paths and the smaller power consumption. Even better, 3-D IC makes the heterogeneous integration possible. The market research has also predicted that 3-D IC technology will be widely used in the smart phones, laptops and other portable products. In addition, memory stacking and SSD may also be the important 3-D IC applications. In this article, we will briefly describe the 3-D IC technology based on Through-Silicon Via (TSV). Moreover, we also introduce the research and results of 3-D IC in ICL, ITRI. Although, currently many companies and parties are actively involved in the development of 3-DIC technology, 3-D IC is still far away from the matured technology. We need the help and cooperation from IC design houses, foundries, OSAT (Outsourced Semiconductor Assembly and Test) and academic research units to overcome the challenges.