時脈樹合成是三維晶片設計問題中一個重要且非常具有挑戰性的問題。三維時脈樹的設計必須確保時脈訊號藉由穿矽孔在不同層間傳遞時的偏斜和延遲最小。然而，在之前相關三維時脈樹的研究中，並沒有考慮到穿矽孔的可靠度問題。因此，三維時脈樹架構中所使用的任何穿矽孔瑕疵，都可能使整個晶片功能發生問題。一個直覺解決的方式是利用雙重穿矽孔，但代價會產生相當大的額外面積需求，使得此方式在實際大設計中並不實用。在此篇論文中，我們提出一個可利用於三維時脈樹架構中的穿矽孔容錯架構。此一架構主要利用三維時脈網路設計中，堆疊前用來測試用的多餘時脈樹，使得容錯所需的額外面積非常小。應用在實際工業界的設計上，我們所提出的穿矽孔容錯架構跟雙重穿矽孔的技術比較起來，可節省約61%的額外面積，並且提升3.9%的良率。

Clock tree synthesis is one of the most important and challenging problems in 3-D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew and latency. While there are a few related works in literature, none of them considers the reliability of TSVs. Accordingly, the failure of any TSV in the clock tree yields a bad chip. The naive solution using double-TSV can alleviate the problem, but the significant area overhead renders it less practical for large designs. In this paper, we propose a novel TSV fault-tolerant unit (TFU) that can provide tolerance against TSV failures in a 3-D clock network. It makes use of the existing 2-D redundant trees designed for pre-bond testing, and thus has minimum area overhead. Compared to the double TSV technique, the 3-D clock network constructed by our TFUs can achieve 61% area reduction with 3.9% yield rate improvement on an industrial case. To the best of the authors' knowledge, this is the first practical work in literature that considers the fault tolerance of a 3-D clock network.