這篇論文提出了一個晶片與晶片之間以全標準元件實現的時脈校正電路與方法。這個方法的特色在於其鎖定與晶片間互連的穿矽孔（或延遲線）的延遲時間是沒有關係的。換言之，它會以相互補償延遲時間的方式達到鎖定的效果。先前用來達到兩個時脈同步的提案必須預先量測通過穿矽孔的延遲時間，決定補償所需要的延遲時間，才能開始進行補償的動作。在此我們提供一個更便利、更準確的方法，達到晶片間或遠距離的時脈校正，並且透過下線來驗證整個設計。這樣的電路是由我們首先提出，完全以標準元件合成，因此易於製程的轉移為其優勢。我們以90奈米製程來驗證此電路，量測的結果顯示：在600MHz的工作頻率（週期為1660ps）下得到10.6ps(0.6%)的相位錯誤差與1.76mW的功耗。

This paper presents a die-to-die clock synchronization method, which is independent of inter-die interconnect delay, through a two-phase all digital delay locked loop (2-P ADDLL) and a dual locking mechanism. The method can be used to maintain a global clock signal between dies, thereby enabling the synchronous 3-D IC design methodology. Unlike previous methods, ours does not need to know a priori the inter-die interconnect delay. This is extremely important since the delay is often subject to change in the 3-D IC and thus is hard to predict. Such a method has several other benefits. For example, it can accommodate the ever-increasing process variation easily through its tracking ability. Silicon measurements of a test chip in a 90nm CMOS technology show that at a clock frequency of 600MHz, the phase error can be locked in 10.6ps (0.6% phase error) with peak-to-peak jitter of 9.8ps and power consumption of only 1.76mW.